Fully delay and multiple stuck-at fault testable sequential circuit design
In this paper we show that it is possible to derive a sequential circuit either from a transition table or from a State Transition Graph (STG), so that the sequential circuit has the short test detecting all multiple stuck-at faults at gate poles of the circuit, and delay of each circuit path is detectable
Download file
Counter downloads: 293
Keywords
конечный автомат, граф переходов, неисправности задержек путей, кратные константные неисправности, монотонные функции, finite state machine (FSM), state transition graph (STG), path delay faults (PDFs), multiple stuck-at faults, monotonous functionsAuthors
| Name | Organization | |
| Matrosova Anjela Yu. | Tomsk State University | mau11@yandex.ru |
| Ostanin Sergey A. | Tomsk State University | ergeiostanin@yandex.ru |
| Nikolaeva Ekaterina A. | Tomsk State University | nikolaeve-ea@yandex.ru |
| Kirienko Irina E. | Tomsk State University | irina.kirienko@sibmail.com |
References
Fully delay and multiple stuck-at fault testable sequential circuit design | Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaja tehnika i informatika – Tomsk State University Journal of Control and Computer Science. 2015. № 4(33).
Download full-text version
Counter downloads: 848