The properties of programmable logic blocks realizing code words of (m, n)-code

This paper deals with a problem of self-testing checker (STC) design for a subset of code words of (m, n)-code. A self-testing (m, n)-code checker is used in concurrent error detection (CED) technique under suggestion that all code words appear on its inputs. It is supposed that either the circuit or the checker may be fault but not both. In practice only some code words are reachable on outputs of self-checking circuit and consequently on inputs of self-testing checker. In that case some faults of the checker can be undetectable as the proper code words do not appear on the circuit outputs. As a result, wrong code word on the fault self-checking circuit may be not detected by the checker. That is why it is necessary to provide the self-testing property of the checker for the corresponding sub-set of all code words of the same weight. A method of a self-testing (m, n)-code checker design based on using of CLBs was proposed before. CLBs were supposed to be realized in the frame of the LUT-technology and, hence, could be programmed to implement any Boolean functions of a fixed number of variables. The set V of the checker faults includes all multiple stuck-at faults at the CLB inputs. Only one CLB in the checker can be fault. The self-testing checker has to satisfy the following conditions: 1) if a non-code word appears at the output of the circuit (or at the input of the checker) then the checker should give the appropriate signal; 2) any fault from the set V should be detected in the set of all code words. It means that there should be a code word for which the fault manifests itself at the checker outputs. The self-testing checker has two outputs with the following meanings of signals combinations: a) (01) or (10) mean that the input word is a word of the (m, n)-code and the checker is faultless; b) (00) or (11) mean that either the input word is non code one or the checker is fault. To represent all possible (m, n)-code words, a special decomposition formula was proposed m Dm (X) = E Dg (X'D"" (X). i=0 The decomposition formula is used several times. The result of its application is represented by the corresponding tree. The design of a self-testing checker for arbitrary number l of code words of (n, m)-code is based on the decision of two tasks: 1. Getting representation of l code words by sum of code words presented by proper sub-tree of the tree. 2. Deriving the self-testing checker based on the received representation. Here the second task of the problem is considered. The properties of programmable logic blocks which inputs receive a sub-set of code words of special type are described. Based on the properties the algorithm of analysis of the given sub-set is developed. It allows finding out if it is possible to design a self-testing checker or not.

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