Simplification of fully delay testable combinational circuits and finding of PDF test pairs | Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaja tehnika i informatika – Tomsk State University Journal of Control and Computer Science. 2017. № 39. DOI: 10.17223/19988605/39/11

Simplification of fully delay testable combinational circuits and finding of PDF test pairs

Fully delay testable circuits obtained by covering ROBDD nodes with Invert-AND-OR sub-circuits and Invert-AND-XOR sub-circuits implementing Shannon decomposition formula are considered. Algorithms of finding test pairs for robust testable PDFs and validatable non robust testable PDFs of resulted circuits have been developed. Experimental results demonstrate essential simplification of suggested circuits in contrast to fully delay testable circuits obtained by covering each ROBDD node with only Invert-AND-XOR sub-circuit.

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Keywords

path delay fault (PDF), robust testable PDF, validatable non robust testable PDF, Binary Decision Diagram (BDD), design for testability, робастно и не робастно тестируемые неисправности задержек путей, ROBDD-графы, контролепригодный синтез

Authors

Name	Organization	E-mail
Matrosova Anjela Yurievna	Tomsk State University	mau11@yandex.ru
Mitrofanov Evgenii Vladimirovich	Tomsk State University	qvaz@yandex.ru
Shah Toral	Indian Institute of Technology	Shah@yandex.ru

Всего: 3

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