A Fault-tolerant Sequential Circuit Design for Stuck-at Faults and Path Delay Faults | Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaja tehnika i informatika – Tomsk State University Journal of Control and Computer Science. 2017. № 41. DOI: 10.17223/19988605/41/8

A Fault-tolerant Sequential Circuit Design for Stuck-at Faults and Path Delay Faults

This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has only one self-checking sequential circuit, normal (unprotected) sequential circuit and not self-testing checker. It is proved the reliability properties of the suggested scheme both for single stuck-at faults (SAFs) at gate poles and path delay faults (PDFs), transient and intermittent. It is supposed that each next fault appears when a previous one has disappeared. Estimations of the schemes complexity are discussed.

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Keywords

fault-tolerant scheme, sequential circuit, self-checking circuit, stuck-at fault, path delay fault, soft error, отказоустойчивая схема, последовательностная схема, самопроверяемая схема, константная неисправность, неисправность задержки пути, нерегулярная ошибка

Authors

Name	Organization	E-mail
Matrosova Anjela Yurievna	Tomsk State University	mau11@yandex.ru
Ostanin Sergey Alexandrovich	Tomsk State University	sergeiostanin@yandex.ru
Kirienko Irina Evgenievna	Tomsk State University	irina.kirienko@sibmail.com
Nikolaeva Ekaterina Alexandrovna	Tomsk State University	nikolaeve-ea@yandex.ru

Всего: 4

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