Synthesis of concurrent error detection systems of multioutput combinational circuits based on Boolean complement method

One of approaches to the logical combinational circuits reliability increase is addition of fault detection means and organization of concurrent error detection systems. Two basic structures are often used for this purpose. First, one realizes the idea of check bits calculation: outputs of diagnostic object correspond to the data vector; test circuit is built by the principle to add the data vector with the check vector of previously chosen error detection code. Second, one realizes the idea of logical complement of the vector formed on the outputs of diagnostic object to the code word of previously chosen non-separable code. The second structure has an advantage: it allows transformation of any number of the original vector bits; thereby it gives the possibility to minimize the structural redundancy of diagnostic system and achieve the self-checking property simpler. The paper is devoted to the features of synthesis of concurrent error detection systems of multioutput combinational circuits based on Boolean complement method. The features of technical implementation of unchangeable test circuit parts are analyzed; they are synthesized using Boolean complement method for combinational circuits with any number of outputs. It is shown that the most effective approach for the circuits with lot of outputs is distribution of them by groups with subsequent check using constant-weight codes with small code vector lengths (m < 6). It is determined that the way of technical implementation with minimal redundancy of unchangeable test circuit part is the distribution of outputs on four-element subsets; every subset is checked using constant-weight code "2-out-of-4" or self-checking two-rail checker. Features of technical implementation of concurrent error detection system based on constant-weight codes are stated.

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