Experimental studies of one-bit and one weighted bit sum codes within concurrent error detection systems

In concurrent error detection (CED) system tested logic circuit F(x) with m outputs are equipped with special check circuit, that allows indirectly to determine its structure faults by the results of analysis of calculated function values. There are reference logic block G(x) and totally self-checking checker within the structure of check circuit. Block G(x) calculates k values of reference functions, and checker registers the conformance of operational and reference functions values during the CED system operation. In general, CED system bases on pre-selected code with small redundancy, focused on error detection in data vectors. Typically the sum codes, or (m,k)-codes (with m and k - lengths of data and check vectors of the code) are used. One of the promising modifications is building the (m,k)-code, where single weight factors are assigned to m-1 bit of data vector, and to one of them - the weight factor w,>2. The author refers to them as WS(m,k,wi)-code. This paper highlights the results of using these codes within CED systems of reference combinational logic circuits. This article provides the results of experimental studies of WS(m,k,wi)-code within CED systems with the set of reference combinational circuits LGSynth'89. It demonstrates the analysis of features of this class of codes by error detection at the outputs of tested units, as well as the assessment of weighted bit position weight factor value influences on the performances of CED system equipment redundancy. From the error detection performance perspective at the outputs of tested circuits the value of weight factor wi can be selected from the set w_i е [2;3;...;m] (characteristics of codes with wi > m are unchanged). Thus, one bit can be weighted m - 1 number of ways, that during the weighting one by one each of the bits will give the following number of codes: ^NWS(m,k,w) =^{(m - l)m} = ^{m2 - m}. Therefore, taking into account the famous Berger code, we get that the circuit with m outputs is possible to control by using this number of sum codes with the different error detection performances: ^N(m,k) = ^{m - m} + ¹ The article also refines the well-known characteristics of weight-based sum codes in the case of forming the nonregular number of data vectors at the outputs of real logic circuits. The key characteristics among others of WS(m,k,wi)-codes, registration of which is reasonable during the synthesis of CED systems of real combinational circuits, are the following: I. WS(m,k,wi)-codes, regardless of weighted bit in data vector and the weight factor value, detect any unidirectional errors in data vectors. 2. With the certain value of weight factor, regardless of weighted bit in data vector, WS(m,k,wi)-codes detect all asymmetrical errors in data vectors (this characteristic provided for sure when wi>m, however for real circuits the exclusion of asymmetrical errors from the undetectable ones can be achieved also under the lower values of wi). 3. When weight factor w,>2 the minimum number of undetectable symmetrical errors are achieved for the given weighted bit of data vector, and for the different weighted bits this minimum number is different. The author obtained the following basic experimental results. Since codes under consideration detect any unidirectional errors, it is reasonable to make its comparison based on its ability to detect non-unidirectional distortions. Berger codes do not detect the significant part of non-unidirectional errors: for 7 combinational circuits this value is 100%, and the average value for the sample - 73.667%. WS(m,k,wi)-codes have improved characteristics for error detection: for 8 combinational circuits any non-unidirectional errors were detected, and at average - the fraction of undetectable errors was decreased in comparison with Berger codes to 10.311%. For about all combinational circuits the doubled number of errors at the outputs was obtained, in comparison with Berger codes; the average is 20.353% (5 times increasing the number of detectable distortions). The results obtained provide good prospects for implementation of WS(m,k,w,)-codes within technical diagnostics problem solving, and, first of all, for CED systems organization. The article offers an algorithm of sum code selection considering the maximum error detection at the outputs of tested unit and the possibility of decreasing the equipment redundancy of CED system for the specific weighted bit. Using of WS(m,k,w,)-codes for CED systems synthesis allows to increase the number of ways for its technical implementation and to provide the systems structure, that will meet pre-determined requirements for error detection and equipment redundancy.

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