Deriving tests for digital circuits at lower and higher abstraction levels

In this paper, we propose an approach for deriving complete test suites for logic circuits, which detect both low-level faults and high-level faults. For deriving low level tests, we consider logic circuits described in BLIF format and a mutation approach is used for the test derivation. First, logic circuit mutants with respect to considered faults are derived and test sequences, for distinguishing the reference and mutated circuits are then constructed (if such a sequence exists). For deriving a distinguishing sequence, a logic synthesis and verification software tool called ABC is used. Three types of faults in logic circuits are considered: those are Single Stuck-At Faults (SSF) considered in many references. We also consider Single Bridge Faults (SBF), which occur when one of the intermediate inputs becomes wrongly wired. The last considered faults type is a Hardly Detectable Faults (HDF) when a single gate of the circuit is replaced with another gate that has slightly different behavior. Test suite is derived by covering all such mutants. For deriving higher level tests, we use a finite state machine (FSM) and according to our experiments test suites derived based on logic circuits cover 64% of transitions of the corresponding FSM on average. We propose to complete logic circuit based test suites with sequences, which allow to cover previously uncovered transitions of the corresponding FSM and specify the fault model for which augmented test suites are complete. Correspondingly, augmented tests are complete with respect to the mutations of a logic circuit as well as with respect to output faults of a higher-level FSM model.

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