Assessment of the quality of diagnostic tests on models of digital devices ISCAS

A methodology for evaluation of the quality of diagnostic tests on models of digital devices (DD) standardised by the IEEE International Symposium is considered. The need to develop such a technique is caused by the intensive process of introducing electronic products into all areas of human activity. These electronic products (digital devices) need to be designed, manufactured and operated, keeping them in a good working state. At each stage of the life cycle of the DD it is necessary to know their technical status (correct or faulty), which is ensured by monitoring and diagnostic, apply the tests and to analyze the DD reaction to it. Creating effective tests is one of the urgent tasks of modern diagnostics. The effectiveness of tests depends on the algorithms used to create them. Now there are many such algorithms, whose products (tests) require analysis and evaluation of quality. For an objective analysis and evaluation of algorithms experts developed test circuits of DD (ISCAS [1]), standardised by the IEEE International Symposium on Circuits and Systems. Using these test circuits, it is possible in the computer-aided design of electronic devices (Electronic Design Automation, EDA) to create algorithmic models of the ISCAS of DD, which are almost the same as their actual physical models. Modern EDA, as a rule, allows you to create algorithmic models in the languages of the description of electronic circuits Verilog or VHDL. Previously developed models on VHDL can be translated to Verilog with subsequent compilation, which ensures their compatibility. At the same time, it becomes possible to effectively explore the various approaches and ideas underlying the test synthesis algorithms for complex DD. In addition, this approach allows us to evaluate the technical DD state to create a convenient apparatus for obtaining, storing and analyzing the results of diagnostic experiments. It is very important that these results can be presented in various convenient forms for the researcher (bit array, binary vector, graphic images, etc). All this makes EDA the basis for the development of a new promising methodology that solves a wide range of problems of technical diagnostics of complex DD. The capabilities of this technique were illustrated on standard ISCAS сircuits «c17» and «c432». For ISCAS circuits the proposed methodology may include the following steps: selection of a test circuit from ISCAS; data input (schematic diagram or description of DD in Verilog, VHDL) and parameters in the simulation environment (for example, Quartus II [2], ModelSim [3], Icarus Verilog (Iverilog) [4], etc.); development on the base of analyzed algorithms tests for control and diagnostic in the simulation environment; compilation and debugging of the created DD model and tests; diagnostic experiments with a well-functioning model DD and tests in the simulation environment, as well as visualization of the results of diagnostic experiment; analysis of the results and placing the results in open access to ensure the possibility of their verification and repetition [5].

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