The synthesis of integrated check circuits based on the boolean complement method with the preliminary compression of the operating functions signals

Modern devices and control systems are increasingly implemented on the basis of microelectronic and microprocessor technology, which includes a large number of elementary components with their dense location relative to each other. The natural aging of components, external destabilizing factors, electromagnetic and radiation effects, etc. lead to the occurrence of failures and resistant faults. The use of microelectronic and microprocessor devices in critical application systems requires the fault parry, high fault-tolerance and survivability. The methods of the checkable and self-checking digital devices synthesis are widely used for this purpose in the control systems development. Often, the synthesis of self-checking digital devices uses methods of coding theory and, directly, uniform block codes with low redundancy. Their use in many cases makes it possible to synthesize simpler self-checking devices than in duplication. The traditional structure of a self-checking device is a structure that includes a source block, an additional block that generates the values of special check functions, as well as a checker that checks the correspondence of the values of the operating functions of the source block and the check functions of the additional block. However, the author's research shows that an alternative structure that implements the idea of Boolean complement has more «flexibility». In this structure, in addition to the source and additional blocks, a cascade of transformation elements (two-input elements of addition by modulo two) is also used. It makes it possible to convert the values of all (or part) of the operating functions of the source block into the code word of the preselected uniform binary code, or into the values of functions belonging to one of the classes of Boolean functions, for example, the class of self-dual functions. The Boolean complement method due to a large number of variations in signal transformations on the correction elements makes it possible to get a large number of the additional block implementations, as well as more simply provide the self-checking of the integrated check circuit itself (conversion elements and the checker). In this paper, the reader's attention is focused on the application of the preliminary signal compression with subsequent control of the vector of compressed functions based on constant-weight codes in the organization of integrated check circuits using the Boolean complement method. In this case, it is assumed to use the basic structure, which is constructed for six outputs of the controlled device. Signals from six outputs are compressed on three elements of addition by modulo two and make it possible to form a three-bit vector of compressed functions <φ₃ φ₂ φ₁>. Then the vector <φ₃ φ₂ φ₁> is converted using the Boolean complement block to a four-bit vector 4 h₃ h₂ h₁>, which belongs to the constant-weight code “1-out-of-4” and is fed to the inputs of the checker of this code. In this case, the h₄ function is formed directly by an additional block without any special transformation. This approach to the organization of the integrated check circuit makes it possible not only to minimize the number of check subcircuits from the "six" outputs of the source block, but also to significantly increase the detection ability of the structure. This is achieved by most frequently generating one value at the input h₄ of the tester and zero values at the other inputs, because in this case any distortion in the vector <φ₃ φ₂ φ₁> will be fixed by the checker. The authors show why the new structure will have an improved detection ability compared to other methods of the integrated check circuit synthesis using the Boolean complement method. The article also provides the generalized structures for the organization of integrated check circuits based on constant-weight code “1-out-of-n”. The article severally highlights the features of selecting the groups of compressed outputs and a method that makes it possible to select the groups of compressed outputs in such a way that each such group eliminates masking errors on the inputs of elements of addition by modulo two. The method is based on searching for groups of dependent and independent outputs to compress the signals only in groups of independent outputs. The article describes a structured approach to searching for groups of compressed outputs. Examples are provided to illustrate this approach. According to the authors, the use of the Boolean complement method with the scheme of preliminary compression of the signals is promising for solving problems of synthesis of self-checking digital systems.

Keywords

Authors

References