Matrix multiplier architecture for QC-LDPC code with minimum FPGA block RAM resource using

Forward error correction coding based upon iterative decoding are widely used in modern communication systems. Low Density Parity Check codes (LDPC) is one of it. These codes have increased requirements for the processing performance of modem equipment, since they require a large number of decoding iterations to obtain a good coding gain. The LDPC check matrix can be arbitrary and vary with other encoding parameters in general. So, decoding such codes is performed sequentially symbol by symbol and does not allow high throughput from the decoder. There are some classes of LDPC codes that have good capabilities for paralleling processing and changes in code characteristics on fly. Quasi-Cyclic Low Density Parity Check codes (QC-LDPC) is one of it. The check matrix of such codes is a shift matrix based upon base matrices array and has clear structure. It makes possible to increase the performance of the decoder due to its natural parallelism at the level of base matrices. However, requirements of communication system performance can be so high that despite this feature, decoder performance may not be sufficient. An additional level of parallelism based upon elements of the base matrices is required. It’s realized through a matrix multiplier unit based on block memory. The classic solution of it involves the use of a large amount of FPGA memory blocks used in a non-optimal mode. Each memory unit use an own write/read address generator. Multiplication by shift matrix is carried out due to barrel shifter. This architecture provides high throughput but requires a lot of FPGA resources. Especially, the block ram units which is one of most critical FPGA resources. There is an alternative solution for architecture of matrix multiplier. The proposed solution is based upon one larger-width memory unit with single read/write address generator, bit shifter and registers for intermediate data storing. This solution has a similar bandwidth as classic one and requires a significantly smaller number of FPGA resources. Proposed solution shows reduction of FPGA block memory and LUT using up to 4 and 2 times respectively and obtain increased performance due to clock frequency increase up to 5-6% at same time. Moreover, the advantage of it is the ease of changing base matrix size and the shift value. Therefore, the proposed solution is recommended for constructing high throughput decoders with adaptive coding support.

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