FPGA implementation of floating-point LMS adaptive filters using high-level synthesis

This paper considers how to use high-level synthesis (HLS) tools for FPGA implementation of floatingpoint least mean square (LMS) adaptive filters. The essence of high-level synthesis is to transform a source code written in a programming language like С or C++ to an RTL code which is later used for creating an IP module. High-level synthesis provides a possibility to concentrate on the algorithm and architecture of a scheme being developed, while FPGA resources and their connectivity are determined automatically. This is especially important when developing adaptive filters on FPGAs because the automated FPGA design of adaptive filters is not supported in IDEs just as it is done for FIR filters. In this paper, the source code of the LMS adaptive algorithm is written in C++ language. In the main function of the source code, input, output, and internal variables are presented as single-precision, floating-point numbers in line with IEEE 754 standard. Samples of the input signal and desired signal are the input variables, while samples of the output signal and error signal are the output variables. During a high-level synthesis procedure, input and output variables of the main function are transformed into input and output ports of the IP module being synthesized. HLS is carried out under the control of synthesis settings and directives formed separately from the source code. A combination of the source code with different synthesis settings and (or) directives leads to different results, each of which is called a project solution. In this paper, the same source code of the LMS adaptive algorithm is used to create two solutions of the LMS adaptive filter under the control of two different sets of synthesis settings and directives. Within each solution, the LMS filters were synthesized of the order ranging from 32 to 512 coefficients. For each set of synthesis settings, the minimum clock frequency was set equal to 100 MHz. The other synthesis settings and directives were left default for the first solution, while for the second one, the loop of operations contained in the source code was pipelined. That is, in the first LMS filter solution, the next loop iteration starts after the previous one has ended. In the second solution, the next iteration starts five cycles after the previous one, whereas in both solutions the whole iteration needs twenty clock cycles. In the LMS algorithm, the loop contains the major part of calculations, including filter coefficients updating and convolution between the input signal and the current impulse response of the filter. Therefore, pipelining of the loop has enabled the latency of the LMS algorithm to be significantly reduced, namely by more than 70%. It has been shown that for both solutions, operations are scheduled into clock cycles similarly, and the basic operations such as multiplication, addition, and RAM reading and writing are performed in the same number of cycles. The order of operations is, in general, the same for both solutions. Besides timing characteristics, resource utilization has been assessed for both solutions. It has been shown that the loop pipelining affects the resource utilization insignificantly: the FF and LUT utilization increases by not more than 31% and 10%, respectively. The increased utilization of FFs and LUTs in the second solution is caused by the more complicated control logic and by the storage of more intermediate results of calculations. The utilization of DSP blocks and block RAMs is the same for both solutions. It has also been shown that when increasing the filter order, the utilization of memory grows up in proportion to it, but the utilization of DSP blocks remains unchanged, and the utilization of FFs and LUTs increases very little. High-level synthesis was carried out in Vivado HLS 2018.3. The LMS filter IP modules are intended to be implemented on Xilinx XC7A200tfbg-1 FPGA. The author declares no conflicts of interests.

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