Determining security key the hardware for digital devices
The features and reliability of logical coding of combinational circuits are considered. An algorithm for breaking the code of combinational circuits is proposed, based on the description of the encoded structure by the resolution function and the reduction of the problem to CNF satisfiability. The initial data for decoding the structure of a digital device are the structural implementation of the encoded circuit, obtained, for example, by the reverse engineering method (prototype design), as well as an activated physical sample of the integrated circuit, the correct key value is loaded into the memory protected from unauthorized access. This sample can be used as a black box model. The main idea ofkey breaking is to solve the problem without resorting to research on a large range of values of input and output variables. Contribution of the authors: the authors contributed equally to this article. The authors declare no conflicts of interests.
Keywords
digital device,
logical encoding,
decoding,
resolution function,
CNF satisfiabilityAuthors
Zolotorevich Ludmila A. | Belarusian State University of Informatics and Radioelectronics | lazolotorevich@gmail.com |
Ilyinkov Valery A. | Belarusian State University of Informatics and Radioelectronics | v.ilyinkov@gmail.com |
Всего: 2
References
Золоторевич Л.А. Аппаратная защита цифровых устройств // Вестник Томского государственного университета. Управ ление, вычислительная техника, информатика. 2020. № 50. С. 69-78.
Subramanyan P., Ray S., Malik S. Evaluating the security of logic encryption algorithms // IEEE International Symposium on Hardware Oriented Security and Trust (HOST). 2015. P. 137-143.
Rajendran J., Sam M., Sinanoglu O., Karri R. Security analysis of integrated circuit camouflaging // ACM SIGSAC Conference on Computer & Communications Security. Germany, Berlin. 04-08 November 2013. P. 709-720.
Roy J.A., Koushanfar F., Markov I.L. EPIC: Ending piracy of integrated circuits // IEEE Computer. 2010. V. 43, № 10. P. 30-38.
Yasin M., Rajendran J., Sinanoglu O., Karri R. On improving the security of logic locking // IEEE TCAD. 2016. V. 35, № 9. P. 1411-1424.
Rajendran J., Pino Y., Sinanoglu O., Karri R. Logic encryption: a fault analysis perspective // Proc. IEEE/ACM DATE. 2012. P. 953-958.
Rajendran J. et al. Fault analysis-based logic encryption // IEEE Trans.Comput. 2015. V. 64, № 2. P. 410-424.
Dupuis S., Ba P., Natale G.D., Flottes M., Rouzeyre B. A novel hardware logic encryption technique for thwarting illegal over production and hardware trojans // IEEE 20th International On-Line Testing Symposium (IOLTS). 2014. P. 49-54.
Plaza S.M., Markov I.L. Solving the third-shift problem in IC piracy with test-aware logic locking // IEEE Trans.Comput.-Aided Design Integr. Circuits Syst. 2015. V. 34, № 6. P. 961-971.
Lee Y.-W., Touba N. Improving logic obfuscation via logic cone analysis // Proc. Latin-American Test Symposium. 2015. P. 1-6.
Karousos N., Pexaras K., Karybali I.G., Kalligeros E. Weighted logic locking: A new approach for ic piracy protection // IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS). 2017. P. 221-226.
Zolotorevich, L.A. Issledovaniye metodov i sredstv verifikatsii proyektov i generatsii testov MES / L.A. Zolotorevich // Sbornik nauchnykh trudov vserossiyskoy nauchno-tekhnicheskoy konferentsii "Problemy razrabotki perspektivnykh mikroelektronnykh sistem - MES-2006". Red. A.L. Stempkovsky. M.: IPPM RAN. 2006. P. 163-168.