FPGA implementation and comparative analysis of sigmoid calculators processing the full argument range in view of symmetry | Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaja tehnika i informatika – Tomsk State University Journal of Control and Computer Science. 2025. № 71. DOI: 10.17223/19988605/71/12

FPGA implementation and comparative analysis of sigmoid calculators processing the full argument range in view of symmetry

This paper implements on FPGA and analyses two sigmoid calculation circuits: the first circuit uses the function’s symmetry, and the second one processes the full argument range. Each circuit is implemented with a bit width of 7 to 10 bits. It is shown that, compared to the second circuit, the first one consumes a smaller amount of resources. But the first circuit uses auxiliary blocks containing long carry chains. sigmoid function; neural network; FPGA; bit-level mapping method; symmetry; critical path. The author declares no conflicts of interests.

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Keywords

sigmoid function, neural network, FPGA, bit-level mapping method, symmetry, critical path

Authors

Name	Organization	E-mail
Ushenina Inna V.	Penza State Technological University	ivl23@yandex.ru

Всего: 1

References

Nurvitadhi E., Venkatesh G., Sim J., Marr D., Huang R., Ong Gee Hock J., Boudoukh G. Can FPGAs beat GPUs in accelerating next-generation deep neural networks? // Proc. of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’17), 22-24 February, Monterey, CA, USA. 2017. P. 5-14.

Шашев Д.В., Шатравин В.В. Реализация сигмоидной функции активации с помощью концепции перестраиваемых вычислительных сред // Вестник Томского государственного университета. Управление, вычислительная техника и информатика. 2022. № 61. С. 117-127. doi: 10.17223/19988605/61/12.

Шипицин С.П., Ямаев М.И. Развитие аппаратно-ориентированных нейронных сетей на FPGA и ASIC // Вестник Пермского национального исследовательского политехнического университета. Электротехника, информационные технологии, система: управления. 2019. № 31. С. 177-192.

Tommiska M.T. Efficient digital implementation of the sigmoid function for reprogrammable logic // IEE Proceedings-Computers and Digital Techniques. 2003. V. 150 (6). P. 403-411. doi: 10.1049/ip-cdt:20030965.

Ушенина И.В. Реализация на современных ПЛИС вычислителя сигмоидной функции активации нейронных сетей таблич ным методом // Вестник Томского государственного университета. Управление, вычислительная техника и информатика. 2024. № 69. С. 124-133. doi: 10.17223/19988605/69/13.

Li X.J., Li L. IP core based hardware implementation of multi-layer perceptrons on FPGAs: a parallel approach // Advanced Mate rials Research. 2012. V. 433. P. 5647-5653. doi: 10.4028/www.scientific.net/AMR.433-440.56471.

Yang T., Wei Y., Tu Z., Zeng H., Kinsy M.A., Zheng N., Ren P. Design Space Exploration of Neural Network Activation Function Circuits // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2019. V. 38 (10). P. 1974-1978. doi: 10.n09/TCAD.2018.2871198.

Rajput G., Raut G., Chandra M., Vishvakarma S.K. VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators // Microprocessors and Microsystems. 2021. V. 84. Art. 104270. doi: 10.1016/j.micpro.2021. 104270.

Saranya S., Elango B. Implementation of PWL and LUT based approximation for hyperbolic tangent activation function in VLSI // Proc. of 2014 International Conference on Communication and Signal Processing, 03-05 April, Melmaruvathur, India. 2014. P. 1778-1782.

Omondi A.R., Rajapakse J.C. FPGA implementations of neural networks. New York : Springer, 2006.

Thasnimol V.S., George M.A. Hardware Accelerator Implementation of Multilayer Perceptron // Proc. of Congress on Intelligent Systems (CIS 2020). 2021. V. 1. P. 107-119.

Vu H.M., Thang H.V. A Customized Hardware Architecture for Multi-layer Artificial Neural Networks on FPGA // Proc. of Fourth International Conference on Information Systems Design and Intelligent Applications, India. 2018. P. 637-644.

Holt J.L., Hwang J.N. Finite precision error analysis of neural network hardware implementations // IEEE Transactions on Computers. 1993. V. 42 (3). P. 281-290. doi: 10.1109/12.210171.

GW2AR series of FPGA Products : Data Sheet. URL: https://cdn.gowinsemi.com.cn/DS226E.pdf (accessed: 10.09.2024).

Configurable Function Unit (CFU) : User Guide. URL: https://www.gowinsemi.com/upload/database_doc/1777/document/62e351486e153.pdf (accessed: 10.09.2024).