About changing arbitrary test pairs detecting robust testable PDFs for ones consisting of neighbor Boolean vectors
Detection of robust testable path delay faults is an important step in testing of high-performance integrated circuits. It has been previously shown that using test pairs of Boolean vectors adjacent in the input path variable allows a significant reduction of power consumption when testing such faults. These test pairs are derived from path Boolean difference/ In this paper, we investigate a possibility of replacing of arbitrary test pairs that detect robust testable path delay faults with test pairs consisting of Boolean vectors adjacent in the input path variable. Such replacement can be useful when forming test sequences from arbitrary test pairs aimed at reducing power consumption. Contribution of the authors: the authors contributed equally to this article. The authors declare no conflicts of interests.
Keywords
combinational circuits,
Equivalent Normal Forms (ENFs),
robust testable Path Delay Faults (PDFs),
path Boolean differenceAuthors
| Matrosova Anzhela Yu. | National Research Tomsk State University | mau11@yandex.ru |
| Tychinskiy Vyacheslav Z. | National Research Tomsk State University | tvz.041@yandex.ru |
Всего: 2
References
Липский В.Б., Матросова А.Ю. Свойства пар тестовых наборов, обнаруживающих неисправности задержек путей в логи ческих схемах VLSI высокой производительности // Автоматика и телемеханика. 2015. № 4. С. 135-148.
Bushnell M.L. Essentials of Electronic Testing for Digital, Memory, And Mixed-Signal VLSI Circuits. Hingham, MA : Kluwer Academic Publishers, 2000. 432 p.
Lindgren P., Kerttu M., Thornton M., Drechsler R. Low power optimization technique for BDD mapped circuits // Proc. of the ASP- DAC. 2001. P. 615-621.
Shelar R.S., Sapatnekar S.S. An efficient algorithm for low power pass transistor logic synthesis // Proc. of the ASP-DAC. 2002. P. 87-92.
Gekas G., Nikolos D., Kalligeros E., Kavousianos X. Power aware test-data compression for scan-based testing // 2005 12th IEEE International Conference on Electronics, Circuits and Systems, Gammarth, Tunisia. 2005. P. 1-4.
Tudu J.T., Larsson E., Singh V., Agrawal V.D. On Minimization of Peak Power for Scan Circuit during Test // Test Symposium 2009 14th IEEE European. 2009. P. 25-30.
Kotasek Z., Skarvada J., Strnadel J. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences // IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. 2010. P. 364-369. doi: 10.1109/DDECS.2010.5491750.
Sinduja V., Raghav S., Anita J.P. Efficient don't-care filling method to achieve reduction in test power // 2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI). 2015. P. 478-482.
Hu Y., Fu X., Fan X., Fujiwara H. Localized Random Access Scan: Towards Low Area and Routing Overhead // Proc. of the 2008 Asia and South Pacific Design Automation Conference. IEEE Computer Society Press, 2008. P. 565-570.
Adiga R., Arpit G., Singh V., Satuja K.K., Fujivara H., Singh A.D. On Minimization of Test Application Time for RAS // Proc. 23 International Conference on VLSI design. IEEE, 2010. P. 393-398,.
Matrosova A.Yu., Andreeva V.V., Nikolaeva E.A. Finding Test Pairs for PDFs in Logic Circuits Based on Using Operations on ROBDDs // Russian Physics Journal. 2018. V. 61 (5). P. 994-999.
Matrosova A.Yu , Andreeva V.V., Tychinskiy V.Z., Goshin G.G. Applying ROBDDs for delay testing of logical circuits // Russian Physics Journal. 2019. V. 62 (5). P. 86-94.
Матросова А.Ю., Тычинский В.З. Андреева В.В. Булева разность и обнаружение неисправностей задержек пути // Вестник Томского государственного университета. Управление, вычислительная техника и информатика. 2024. № 66, С. 108-119. doi: 10.17223/19988605/66/11.
