Fault Tolerance SynchronousSequential Design for Transient and Intermittent Faults

Fault tolerance synchronous sequential circuit design for transient and intermittent faults is considered. It is based on doubling self-checking sequential circuit with using checker, OR, AND and MX circuits masking a fault manifestation. Special schemes that are the composition of the circuits are suggested. The schemes provide correct behavior of sequential circuit when any permissible fault occurs in scheme and recovering scheme when a fault disappears. We deal with single stuck-at faults at gates poles and d flip-flops poles of the scheme. Fault tolerance circuit design based on using three sequential circuits demands fault free voting circuit. In our approach any circuit of fault tolerance scheme may be fault. Experimental results showed that the fault tolerance schemes suggested have less overhead than threefold scheme.

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