Checking of circuit implementation of incompletely specified Boolean functions
The task of logical verification iswell studied for the case when both compared descriptions are completely specified and are given as structural representations. This case is reduced to checking on whether two combinational circuits are equivalent. In contrast to that, here the verification task is examined for a case, when desired functionality of the system under design is incompletely specified.
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Keywords
верификация , комбинационная схема , моделирование , verification , combinational circuit , simulationAuthors
| Name | Organization | |
| Cheremisinova L.D. | cld@newman.bas-net.by | |
| Novikov D.Ya. | yakov_nov@tut.by |
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