False path diagnosis

Delay testing has become very important problem with development of nanometer technologies.The objective of delay testing is to detect timing defects degrading the performance of a circuit.Path delay fault model is considered more preferable. To observe delay defects, it is necessaryto generate and propagate transitions in the circuit input. This requires application of a pair ofvectors v1, v2. The first vector v1 stabilizes all signals in the circuit. The second vector v2 causesthe desired transition in the input of a circuit. Take into account that delays of falling transitionand rising transition along of the same path from a primary input to a primary output in a circuitmay be different. In the general case it is necessary a pair of vectors v1, v2 for each kind of transitionsof a path. In accordance with the conditions of fault manifestation single PDFs are dividedinto robust and non robust. PDF is robust if there is a test pair on which the fault manifestationdoes not depend on delays of other circuit paths. PDF is non robust if a manifestation of the faulton a test pair is possible only when all other paths of a circuit are free fault. If delay faults on thecertain path don't manifest themselves neither as robust nor non robust such path is called as falseone. The path must be detected and excluded from consideration. In this paper false path diagnosisis reduced to finding test patterns for stuck-at faults of the proper ENF literals. Test patternsare derived under solving Boolean equations on OR, AND trees that compactly represent ENFs.

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