Selection of the flip-flops for partial enhanced scan techniques | Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaja tehnika i informatika – Tomsk State University Journal of Control and Computer Science. 2012. № 2(19).

Selection of the flip-flops for partial enhanced scan techniques

Structural scan based delay testing is used to detect delay faults. Because of thearchitectural limitations not each test pair v1, v2 can be applied by scan delay testing.That declines test coverage. Partial enhanced scan approach based on selectionof flip-flops was suggested to permit using arbitrary test pairs v1, v2. Theproblem of selection of flip-flops may be solved with applying estimations ofcontrollability and observability of the state variables corresponding to the flipflops.Calculation of controllability and observability estimations is based on 2-length combinational equivalent analyses and PDF testing.

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Keywords

неисправность задержки пути, робастно тестируемый путь, эквивалентная нормальная форма (ЭНФ), Path delay fault (PDF), robust PDF, equivalent normal form (ENF)

Authors

NameOrganizationE-mail
Matrosova Anzhela Yu.National Research Tomsk State Universitymau11@yandex.ru
Melnikov Alexey V.National Research Tomsk State Universityalexey.ernest@gmail.com
Mukhamedov Ruslan V.National Research Tomsk State Universitypredictor@yandex.ru
Ostanin Sergey A.National Research Tomsk State Universityostanin@mail.tsu.ru
Singh VirendraIndian Institute of Technology Bombayvirendra@computer.org
Всего: 5

References

Xu G., Singh A. D. Achieving high transition delay fault coverage with partial DTSFF enhanced scan chains // Proceedings of International Test Conference. 2007. P. 1-9.
Xu G., Singh A. D. Flip-flop selection to maximize TDF coverage with partial enhanced scan // Proc. ATS2007. 2007. P. 335-340.
Wang S. Low overhead partial enhanced scan technique for compact and high fault coverage transition delay test patterns / S. Wang, W. Wei // Proc. ETS2008. 2008. P. 125 -130.
Matrosova А. Random simulation of logical circuits //Automation and Remote Control. 1995. Nо. 1. P. 156-164.
Matrosova A., Lipsky V., Melnikov A., Singh V. Path delay faults and ENF // Proc. EWDT Symposium, Russia, St. Petersburg, September, 2010. P. 164-167.
Matrosova A., Andreeva A., Melnikov A., Nikolaeva E. Multiple stuck-at fault and path delay fault testable circuits // Proc. EWDT Symposium. 2008. P. 356-364.
Ubar R. Multi-valued simulation of digital circuits with structurally synthesized binary decision diagrams // OPA (Overseas Publishers Assotiation) N.V. Gordon and Breach Publishers, Multiple Valued Logic. 2001. V. 4. P. 141-157.
 Selection of the flip-flops for partial enhanced scan techniques | Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaja tehnika i informatika – Tomsk State University Journal of Control and Computer Science. 2012. № 2(19).

Selection of the flip-flops for partial enhanced scan techniques | Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaja tehnika i informatika – Tomsk State University Journal of Control and Computer Science. 2012. № 2(19).

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