Providing full delay testability for circuits obtained by covering of BDDs
Circuits obtained by covering ROBDD and Free BDD nodes with special gate subcircuits are considered. Formulae derived from their structural descriptions are investigated. Based on the results of investigations algorithms of deriving test pairs for robust testable PDFs and validatable non robust testable PDFs of such circuits are developed. It is found out that delay of each circuit path is detectable. Possibilities of cutting calculations under finding the longest circuit paths and compact description of the longest paths are discussed.
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Keywords
неисправность задержки пути, тестопригодное проектирование, BDD-графы, path delay fault (PDF), binary decision diagram (BDD), design for testabilityAuthors
| Name | Organization | |
| Matrosova Anjela Yu. | Tomsk State University | mau11@yandex.ru |
| Kudin Dmitry V. | Gorno-Altay State University | ensase@mail.ru |
| Nikolaeva Ekaterina V. | Tomsk State University | nikolaeve-ea@mail.ru |
| Roumjantseva Elena V. | Tomsk State University | elenakemy@rambler.ru |
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