Lower-power logic synthesis of combinational CMOS circuits

In the paper, the task of synthesis of multilevel circuits in the basis of the static CMOS cell library is considered. The circuits are optimized according to area and mean value of the dissipated power of microcircuit implemented on the CMOS VLSI chip. The case of synthesis of the combinational CMOS circuits is discussed when 1) key schematic solutions, such as clock frequency and supply voltage, are assigned; 2) synchronous implementation of the CMOS circuits is supposed; 3) for the purposes of energy estimation during the synthesis process the static method, based on probabilistic properties of input signals, is used. The estimates of mean value of the dissipated power of the multilevel combinational CMOS circuits on all steps of logic synthesis are proposed. The dynamic power dissipation dominates in the CMOS digital circuits: it accounts for 60%-80% of the overall power dissipation. The dynamic power dissipation is related to charging and discharging node capacitors which is caused by switching signals on circuit nodes. At the stage of logic optimization the majority of the overall energy savings can be achieved by minimizing the switching activities in the circuit. Based on this fact, to estimate variants of circuit optimization on logic level, the quantitative change of switching activity of the resulting (after the variant choosing) circuit is used. It is supposed that a circuit input sequence depends essentially upon its application and can be forecasted by designer on probabilistic level. At that, in addition to functional description of circuit under design, the probabilistic estimates of switching activities of circuit input signals should be specified. Here, the solving problem of logic circuit optimization is based on the assumption that the basic way of power saving during logic design, first of all, reduces the chip area of the circuit implementation. So, in all techniques at all stages of logic design, a ranged criterion is used: the chip area as the first one, and only then a quantitative criterion of circuit switching activity change. In the process of logic synthesis, an abstract form of desired circuit behavior (system of Boolean functions) is turned into a design implementation in terms of the logic gates of the CMOS cell library. The considered approach is based, as overwhelming majority of known synthesis methods, on design process partition into two stages: the technology independent phase, where logic minimization and decomposition is performed on the Boolean functions with no regard to physical properties and the technology dependent phase, where the mapping logic network into a physical CMOS cell library is performed. The first step of technology independent optimization is driven minimization of the Boolean functions in class of disjunctive normal forms (DNFs). In the second step, the two-level network realizing the minimized DNF system is decomposed in the multilevel network of primitive AND and OR gates with restricted numbers of inputs that are predefined by the structures of the basic gates of the target CMOS library. The technology mapping consists in transformation of the multi-level AND-OR network in the target CMOS cell library basis, the mapping is based on structural replacing sub-networks of the initial AND-OR network with cell library instances. In the paper, the modifications of methods, realizing the basic stages of synthesis and optimization of multi-level logic circuits in CMOS cell library basis, are considered. They are minimization of the two-level and multi-level AND-OR networks and mapping the networks into the technological CMOS VLSI basis. To optimize variants for a circuit under design, the comparative look-ahead estimates are proposed which targeted to reducing the average power dissipation of the CMOS circuit and based on expected change of its switching activity.

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