Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method | Applied Discrete Mathematics. Supplement. 2009. № 1.

HomeIssuesPath delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method | Applied Discrete Mathematics. Supplement. 2009. № 1.

Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method

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Authors

NameOrganizationE-mail
Andreeva V. V.Tomsk State Universityavv.21@mail.ru
Matrosova A. Yu.Tomsk State Universitymau11@yandex.ru
Melnikov A. V.Tomsk State Universityalexey.ernest@gmail.com
Morozova A. V.Tomsk State Universityavm@tosksoft.com
Всего: 4

References

Murgai R., Brayton R., Sangiovani-Vincetelli A. Logic Synthesis for Field Programmable Gate Arrays / / Cluver Academic Publisher. 1995. P. 425.
Kohavi I., Kohavi Z. Detection of multiple faults in combinational logic networks / / IEEE Trans. Comput. 1975. No. 6. P. 556-568.
Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method | Applied Discrete Mathematics. Supplement. 2009. № 1.

Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method | Applied Discrete Mathematics. Supplement. 2009. № 1.