Path delay fault test design for circuits obtained by covering ROBDDS with clbs | Applied Discrete Mathematics. Supplement. 2009. № 1.

Path delay fault test design for circuits obtained by covering ROBDDS with clbs

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Authors

NameOrganizationE-mail
Nikolaeva E.A.Tomsk State Universitynikolaeve-ea@yandex.ru
Matrosova A. Yu.Tomsk State Universitymau11@yandex.ru
Всего: 2

References

Drecksler R., Ski J., Fey G. Synthesis of Fully Testable Circuits from BDDs / / IEEE Trans. On CAD. 2001. No. 23(3). P. 440-443.
Матросова А. Ю., Луковникова Е. С. Построение проверяющих тестов для одиночных и кратных неисправностей на полюсах элементов схем, синтезированных на базе ПЛИС (FPGА)-технологий / / Вестник Томского госуниверситета. Приложение. 2007. №23. С. 229-241.
 Path delay fault test design for circuits obtained by covering ROBDDS with clbs | Applied Discrete Mathematics. Supplement. 2009. № 1.

Path delay fault test design for circuits obtained by covering ROBDDS with clbs | Applied Discrete Mathematics. Supplement. 2009. № 1.