Applying ROBDDS for logical circuit delay testing

Increasing functioning frequency and decreasing transistors sizes in high performance logical circuits may result illegal capacities, inductivities, resistances and so on that generate decreasing estimated circuit frequency. These defects cannot be detected by physical methods. The main way of solving the problem is based on delay testing of logical circuits in the frame of path delay fault (PDF) model. In this paper facilities of enhancing of PDF test sequences quality based on applying ROBDDs compactly representing all test pairs of neighbor test patterns for the circuit path are studied. Test patterns (Boolean vectors) are neighbor if they differ by only one component. It is setup that using of these ROBDDs cut the lengths of test sequences more than on 1/3 in comparison with tradition scan test sequences under enhancing test sequence quality. In particular, we derive fully detectable test sequence, decrease their power consumption and peak power values.

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