Modelling of hierarchical memory of non-blocking computer systems

A model is proposed which describes the influence of depth of non-blocking of cache on operational characteristics of two-leveled memory. Operation of hierarchical memory is described by two-staged pipeline. The first stage performs access to cache, and the second, in case of the first stage failure, performs access to operational memory (lower level memory). The operation of the second stage is modelled by Markov's system featuring multi-staged service and discrete timing. Wide range of depth of non-blocking values were investigated for write-back cache and probability-timing characteristics of memory subsystem were found. An average time of access to an object is found, given various parameters of cache.

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