We deal with the combinational circuits derived from BDD descriptions
The circuit is obtained from BDD by its covering with OR, AND, NOT gates. It is shown that gate pole single stuck-at faults of the circuit manifest themselves as unidirectional errors at the circuit outputs. The possibility of using double rail code checker, (m,n)-code checker and Berger code checker for monitoring these outputs is discussed.
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Authors
| Name | Organization | |
| Astafiev Mikhail V. | Tomsk State University | mikle@amv.tsk.ni |
| Matrosova Angela Yu. | Tomsk State University | mau@fpmk.tsu.ru |
References
Закревский А.Д., Балаклей Л.И., Елисеева Н.А. и др. Синтез асинхронных автоматов на ЭВМ. Минск: Наука и техника, 1975. 181 с.
S. Baranov. Logic synthesis for control automata // Dordrecht; Boston; London: Kluwer academic publishers, 1994.
K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli and A.R. Wong. MIS: A multi-level logic optimization program // IEEE Trans. On com puter-aided design. Nov. 1987. Vol. 7. P 1062-1081.
Levin, M. Karpovski On-line self-checking of microprogram control unit // 4 IEEE Intl. On-line testing workshop. Capry, Italy, July 1998. P152-156.
A. Yu. Matrosova. S.A. Oslanin Self-checking synchronous FSM network design // 4"1 IEEE Intl. On-line testing workshop. Capry, Italy, July 1998. P. 162-166.
Астафьев M.B., Левин И., Матросова А.Ю., Синельников В. Синтез самопроверяемых автоматных сетей в базисе ПЛМ // Автоматика и телемеханика (в печати).
Агибалов Г.П., Оранов A.M. Лекции по теории конечных автоматов. Томск: Изд-во ТГУ, 1984. 185 с.
Е Randal Bryant graph-based algorithms for boolean function manipulation // IEEE transactions on computers. August 1986. Vol. C-35, № 8.
A. Yu. Matrosova, S. A. Oslanin Self-checking FSM design with observing only FSM outputs // 4lh IEEE Intl. On-line testing workshop. Capry, Italy, July 1998.Italy, July 1998.