Self-testing combinational (m-n)-code checker design | Vestnik Tomskogo gosudarstvennogo universiteta – Tomsk State University Journal. 2000. № 271.

Self-testing combinational (m-n)-code checker design

A synthesis method of the combinational (m, и)-code checker is developed. The method is based on a decomposition of (m, n)-codes into their subcodes of the less length. As a result all (m, n)-codes are described with the formula depending on a, v, Dp (X ) functions. Here Dp is the sum of products representing all (q, p)-codes, qu..., x„) is a set of (m, n)-codes components. When using FPGA (Field of Programmable Gate Arrays) technology we provide the self-testing properties of the checker for the faults resulted from this technology.

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Authors

Name	Organization	E-mail
Matrosova Angela Yu.	Tomsk State University	mau@fpmk.tsu.ru
Nikitin Konstantin V.	Tomsk State University	mau@fpmk.tsu.ru

Всего: 2

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