Comparative analysis of BCH-codes decoders implementations with parameters (15, 7, 5) using FPGA | Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaja tehnika i informatika – Tomsk State University Journal of Control and Computer Science. 2019. № 46. DOI: 10.17223/19988605/46/12

Comparative analysis of BCH-codes decoders implementations with parameters (15, 7, 5) using FPGA

In this paper we consider the possibility of implementing various decoder of the Bose-Chaudhuri-Hocquingham code (BCH-codes) using field-programmable gate array (FPGA). BCH codes are most common error-correcting codes that are used in many data transmission systems for detecting and correcting errors. BCH-codes with short-length of codewords and with a small number of correcting bits are used in automation systems of production. The code that implemented in the article has the following parameters: - n = 15 - the length of the input code combination; - m = 7 - the length of the information block; - k = 8 - the length of the message control block; - t = 2 - the number of errors, that code corrects; - d = 5 - the maximum Hamming distance between two combinations; - g (x) - 111010001 - the generating polynomial. The paper describes implementations of two simplest decoding methods: a tabular, that based on the application of a table with precalculated errors syndromes; and cyclic, that based on the checking of the weight of remainder of the division of the codeword by the generating polynomial. The simplest implementation is the tabular decoding method. The basis of this method is the table, which stores all possible values of error patterns up to the multiplicity of t. Addresses of error patterns are error syndromes. Having such the table, the decoding process is reduced to selecting a pattern from the table at the address, which is equal to the remainder of the division of the input codeword by the generating polynomial. The error pattern that was selected from the table is summed up modulo two with the input codeword. The corrected codeword arrives to the output of the decoder. The main drawback of this method it is the necessary to build the table and connect additional FPGA resources to store this table. The second decoding method, which is easy to implement, is a cyclic method. This decoding method was designed for codes with the cyclicity property, and it suitable for BCH-codes. This method based on the checking the condition w

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Keywords

помехоустойчивый код, код Боуза-Чоудхури-Хоквингема, табличный метод декодирования, циклический метод декодирования, аппаратная реализация, ПЛИС, error-correction codes, CBH-codes, cyclic decoding methods, table decoding methods, FPGA, hardware-based devices

Authors

NameOrganizationE-mail
Ryzhova Svetlana E.Tomsk Polytechnic Universityr.svet93@yandex.ru
Mytsko Evgeniy A.Tomsk Polytechnic Universityevgenrus70@mail.ru
Malchukov Andrey N.Tomsk Polytechnic Universityjgs@tpu.ru
Всего: 3

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 Comparative analysis of BCH-codes decoders implementations with parameters (15, 7, 5) using FPGA | Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaja tehnika i informatika – Tomsk State University Journal of Control and Computer Science. 2019. № 46. DOI:  10.17223/19988605/46/12

Comparative analysis of BCH-codes decoders implementations with parameters (15, 7, 5) using FPGA | Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaja tehnika i informatika – Tomsk State University Journal of Control and Computer Science. 2019. № 46. DOI: 10.17223/19988605/46/12

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