Delay testable sequential circuit design

Specific physical defects of high performance circuits manifest themselves as path delay faults (PDFs). A pair (v v ) of test patterns is required to detect a PDF. A PDF is robust testable if there exists a test pair on which the fault manifestation does not depend on delays of other circuit paths. A PDF is non robust testable if manifestation of the fault on any test pair is possible only when all other paths of the circuit are fault free. For high quality delay testing it is desirable to detect delay of any path regardless of delays of other paths. Unfortunately providing delay testability is usually connected with injecting additional inputs. But it is not good for practice. In this paper, synthesis of delay testable sequential circuit without additional inputs is suggested. It is based on applying mixed description of sequential circuit behavior. We use ROBDDs for describing fragments of functions depending on input variables and monotonous SoPs for fragments of functions depending on state variables. ROBDD nodes are covered with the original subcircuit from gates. Special decomposition of ROBDDs and monotonous SoP is suggested. Delay testability of such circuit is investigated. It is specified that the PDF of each path of the circuit is detected. Algorithms of deriving test pairs for PDFs are suggested.

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